Computation reordering: A novel transformation for low power DSP synthesis

A novel architectural transformation for low power synthesis of inner product computational structures is presented. The proposed transformation reorders the sequence of evaluation of the multiply-accumulate operations that form the inner products. Information related to both coefficients, which are statically determined, and data, which are dynamic, is used to drive the reordering of computation. The reordering of computation reduces the switching activity at the inputs of the computational units but inside them as well leading to power consumption reduction. Different classes of algorithms requiring inner product computation are identified and the problem of computation reordering is formulated for each of them. The target architecture to which the proposed transformation applies is based on a power optimal memory organization and is described in detail. Experimental results for several DSP algorithms show that the proposed transformation leads to significant savings in net switching activity and thus in power consumption

High Throughput Hardware/Software Co-Design Approach for SHA-256 Hashing Cryptographic Module In IPSec/IPv6

Nowadays, more than ever, security is considered to be critical issue for all electronic transactions. This is the reason why security services like those described in IPSec are mandatory to IPV6 which will be adopted as the new IP standard the next years. In fact E.U. has set the target of moving to IPv6 for about 25% of European e-infrastructures in 2010. However the need for security services in every data packet that is transmitted via IPv6, illustrates the need for designing security products able to achieve higher throughput rates for the incorporated security schemes. In this paper a top-down methodology is presented which manages to increase throughput of SHA-256 hash function hardware design. The higher degree of throughput with limited area penalty and cost is achieved through appropriate Software/Hardware partitioning and design